The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method and system for forming conductive bumping with copper interconnection. Merely by way of example, the invention has been applied to flip chip lead free bumping process for the manufacture of integrated circuit with one or more copper interconnects. But it would be recognized that the invention has a much broader range of applicability.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. Making devices smaller is very challenging, as each process used in IC fabrication has a limit. That is to say, a given process typically only works down to a certain feature size, and then either the process or the device layout needs to be changed. An example is that for increasing packing density in IC, copper/low-k dielectric materials have been rapidly replacing conventional aluminum-alloy/SiO2-based interconnects in integrated circuits to reduce the interconnect delays for faster devices with low power consumption and cost.
Currently for copper interconnect chips, aluminum alloy pad is still widely used. The aluminum alloy pad is easy for wire bonding as an interconnect method and the aluminum pad can act as fuse function. However, the disadvantage of using aluminum pad also can be seen by its high resistance compared to copper, additional mask needed to pattern the bond pad to overcome the difficulties in the aluminum chemical-mechanical planarization (CMP) process, and difficulty in control of cross contamination between aluminum and copper.
From the above, it is seen that an improved technique for processing semiconductor devices is desired.